This invention relates generally to a memory array configuration and more particularly to a memory array configuration that allows simultaneous read and refresh of the memory cells in the array.
In a dynamic random access memory ("DRAM"), data is stored as a logic one or zero by the presence or absence of charge on a capacitor within an individual memory cell. After the data has been stored as charge on the capacitor, the charge gradually leaks off and the data is corrupted. Therefore, a "refresh" cycle must be performed to maintain the integrity of the data. To refresh data in a memory array, the array is typically placed in a read mode to obtain the present data stored in a row of memory cells. Subsequently, this data is used as new input data that is re-written into the row of memory cells, thus maintaining the stored data. An important aspect of the refresh cycle of prior art DRAMs is that a normal read operation must be performed on the row that is being refreshed. No other operation involving a different row in the array can occur simultaneously during the read operation.
A functional block diagram of a typical DRAM, the MT4C4003 1 megabit.times.4 DRAM manufactured by Micron Technology, Inc. of Boise, Id., is shown in FIG. 1. The DRAM memory contains approximately 4 megabits organized into four 1 megabit memory arrays 10A-10D. Circuit block 50 includes sense amplifiers coupled to each column within the memory array to transform charge on the capacitor in the memory cell into a valid logic one or zero. During read and write cycles, each bit in one of the four memory arrays is uniquely addressed through twenty address bits that are entered ten bits (A0-A9) at a time. The RAS signal (row address strobe) latches the first ten bits and the CAS signal (column address strobe) latches the latter ten bits. A read or write cycle is initiated with the WE signal (write enable). The four data inputs/outputs (DQ1-DQ4) are routed through four pins using a common input/output bus controlled by the WE signal and an OE signal (output enable).
In the DRAM of FIG. 1, three types of refresh cycles are available. Two of the cycles involve a specific address provided by the user, along with appropriate RAS and/or CAS signals. A third, "hidden" refresh cycle automatically and internally refreshes the data sequentially in the memory arrays. The hidden refresh cycle is initiated by an appropriate combination of the RAS and CAS signals without specifying an address. However, none of the three refresh cycles allows the user of the DRAM to accomplish any other functions involving different rows within the array while the combination read/refresh cycles are being performed.
Accordingly, a need remains for a memory array configuration that allows a simultaneous read cycle of the memory cells in one row of the memory array and a refresh cycle of the memory cells in another row of the memory array to decrease access time to the stored data.